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1 features ? permanent and reversible software write protection for the first-half of the array ? software procedure to verify write protect status ? hardware write protection for the entire array ? low-voltage and standard-voltage operation ? 1.7 (v cc = 1.7v to 3.6v) ? internally organized 256 x 8 ? two-wire serial interface ? schmitt trigger, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 100 khz (1.7v) and 400 khz (2.7v and 3.6v) compatibility ? 16-byte page write modes ? partial page writes are allowed ? self-timed write cycle (5 ms max) ? high-reliability ? endurance: 1 million write cycles ? data retention: 100 years ? 8-lead jedec soic, 8-lead ultra thin mini -map (mlp 2x3), 8-lead tssop, and 8-ball dbga2 packages description the at34c02b provides 2048 bits of serial electrically-erasable and programmable read only memory ( eeprom) organized as 256 words of 8 bits each. the first-half of the device incorporates a permanent and a re versible software write protection feature while hardware write protection for the entir e array is available via an external pin. once the permanent software write protection is enabled, by sending a special com- mand to the device, it cannot be reversed. however, the reversible software write protection is enabled and can be reversed by sending a special command. the hard- ware write protection is controlled with the wp pin and can be used to protect the entire array, whether or not the software write protection has been enabled. this allows the user to protect none, first-half, or all of the array depending on the applica- tion. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. the at34c02b is avail- able in space saving 8-lead jedec soic, 8-lead ultra thin mini-map (mlp 2x3) , 8-lead tssop, and 8-ball dbga2 packages and is a ccessed via a two-wire serial interface. it is available in 1.7v (1.7v to 3.6v). table 1. pin configurations pin name function a0 - a2 address inputs sda serial data scl serial clock input wp write protect two-wire serial eeprom with permanent and reversible software write protect 2k (256 x 8) at34c02b note: not recommended for new design; please refer to at34c02c datasheet. rev. 3417e?seepr?1/07 8-ball dbga2 bottom view vcc wp scl sda a0 a1 a2 gnd 1 2 3 4 8 7 6 5 8-lead soic 1 2 3 4 8 7 6 5 a0 a1 a2 g nd vc c wp sc l sd a 8-lead tssop 1 2 3 4 8 7 6 5 a0 a1 a2 g nd vc c wp sc l sd a 8-lead ultra thin mini-map (mlp 2x3) bottom view 1 2 3 4 8 7 6 5 a0 a1 a2 gn d v cc wp scl s da
2 at34c02b 3417e?seepr?1/07 figure 1. block diagram absolute maximum ratings* operating temperature..................................?55c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .....................................?65c to +150c voltage on any pin with respect to ground .................................... ?1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma d out /ack logic d out d in a 0 s da g nd a 1 s cl v cc a 2 y dec data word addr/counter serial control logic start stop logic device address comparator serial mux eeprom en comp inc load load r/w h.v. pump/timing data recovery x dec w p write protect circuitry software write protected area (00h - 7fh)
3 at34c02b 3417e?seepr?1/07 pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negat ive edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/page addresses (a2, a1, a0): the a2, a1, and a0 pins are device address inputs that are hardwir ed (directly to gnd or to v cc) for compatibility with other at24cxx devices. when the pins are hardwired, as many as eight 2k devices may be addressed on a single bus system. (device addressing is discussed in detail under ?device addressing,? page 9.) a device is selected when a corresponding hardware and software match is true. if these pins are left floating, the a2, a1, and a0 pins will be internally pulled down to gnd. however, due to capacitive coupling that may appear during customer applicati ons, atmel recommends always connecting the address pins to a known state. when using a pull-up resistor, atmel recommends using 10k ? or less. write protect (wp): the write protect input, when connected to gnd, allows nor- mal write operations. when wp is connected dire ctly to vcc, all write operations to the memory are inhibited. if the pin is left floating, the wp pin will be internally pulled down to gnd. however, due to capacitive couplin g that may appear during customer applica- tions, atmel recommends always connecting t he wp pins to a known state. when using a pull-up resistor, atmel recommends using 10k ? or less. note: 1. this parameter is characterized and is not 100% tested. table 2. at34c02b write protection modes wp pin status permanent write protect register reversible write protect register part of the array write protected v cc ? ? full array (2k) gnd or floating not programmed not programmed normal read/write gnd or floating programmed ? first-half of array (1k: 00h - 7fh) gnd or floating ? programmed first-half of array (1k: 00h - 7fh) table 3. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 100 khz, v cc = +1.7v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v
4 at34c02b 3417e?seepr?1/07 note: 1. v il min and v ih max are reference only and are not tested. table 4. dc characteristics applicable over recommended operating range from: t ai = ?40 c to +85 c, v cc = +1.7v to +3.6v, (unless otherwise noted) symbol parameter test condition min typ max units v cc1 supply voltage 1.7 3.6 v i cc supply current v cc = 3.6v read at 100 khz 0.4 1.0 ma i cc supply current v cc = 3.6v write at 100 khz 2.0 3.0 ma i sb1 standby current v cc = 1.7v v in = v cc or v ss 0.6 3.0 a i sb2 standby current v cc = 3.6v v in = v cc or v ss 1.6 4.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) ? 0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc = 3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc = 1.7v i ol = 0.15 ma 0.2 v
5 at34c02b 3417e?seepr?1/07 note: 1. this parameter is characterized and is not 100% tested. table 5. ac characteristics applicable over recommended operating range from t ai = ?40 c to +85 c, v cc = +1.7v to +3.6v, c l = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter 1.7v 2.7v, 3.6v units min max min max f scl clock frequency, scl 100 400 khz t low clock pulse width low 4.7 1.2 s t high clock pulse width high 4.0 0.6 s t i noise suppression time (1) 100 50 ns t aa clock low to data out valid 0.1 4.5 0.1 0.9 s t buf time the bus must be free before a new transmission can start (1) 4.7 1.2 s t hd.sta start hold time 4.0 0.6 s t su.sta start set-up time 4.7 0.6 s t hd.dat data in hold time 0 0 s t su.dat data in set-up time 200 100 ns t r inputs rise time (1) 1.0 0.3 s t f inputs fall time (1) 300 300 ns t su.sto stop set-up time 4.7 0.6 s t dh data out hold time 100 50 ns t wr write cycle time 5 5 ms endurance (1) 25 c, page mode 1m 1m write cycles
6 at34c02b 3417e?seepr?1/07 memory organization at34c02b, 2k serial eeprom: the 2k is internally organized with 16 pages of 16 bytes each. random word addressing requires a 8-bit data word address. device operation clock and data transitions: the sda pin is normally pulled high with an exter- nal device. data on the sda pin may change only during scl low time periods (see figure 4 on page 7). data c hanges during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 5 on page 8). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place th e eeprom in a standby power mode (see figure 5 on page 8). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero to acknowledge that it has received each word. this happens during the ninth clock cycle. standby mode: the at34c02b features a low-power standby mode which is enabled: (a) upon power-up or (b) after the re ceipt of the stop bit and the completion of any internal operations. memory reset: after an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) clock up to 9 cycles, (b) look for sda hi gh in each cycle while scl is high and then (c) create a start condition.
7 at34c02b 3417e?seepr?1/07 figure 2. bus timing scl: serial clo ck sda: serial data i/o figure 3. write cycle timing scl: serial clock sda: serial data i/o note: 1. the writ e cycle time t wr is the time from a valid stop condition of a writ e sequence to the end of the internal clear/write cycle. figure 4. data validity t wr (1) stop condition start condition wordn ack 8th bit s cl s da
8 at34c02b 3417e?seepr?1/07 figure 5. start and stop condition figure 6. output acknowledge
9 at34c02b 3417e?seepr?1/07 device addressing the 2k eeprom device requires an 8-bit dev ice address word following a start condi- tion to enable the chip for a read or write operation (see figure 10 on page 13). the device address word consists of a m andatory one-zero sequ ence for the first four most-significant bits (1010) for normal re ad and write operations and 0110 for writing to the write protect register. the next 3 bits are the a2, a1 and a0 de vice address bits fo r the at34c02b eeprom. these 3 bits must compare to their corresponding hard-wired input pins. the eighth bit of the device address is the r ead/write operation select bit. a read opera- tion is initiated if this bit is high and a writ e operation is initiate d if this bit is low. upon a compare of the device address, the eeprom will output a ze ro. if a compare is not made, the chip will return to a standby stat e. the device will not acknowledge if the write protect register has been progra mmed and the control code is 0110. write operations byte write: a write operation requires an 8-bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero and then cloc k in the first 8-bit data word. following receipt of the 8-bit data word, the ee prom will output a zero and the addressing device, such as a microcontroller, must te rminate the write sequence with a stop condi- tion. at this time the eeprom enter s an internally-tim ed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (see figure 11 on page 13). the device will acknowledge a write command, but not write the data, if the software or hardware write protection has been enabled. the write cycle time must be observed even when the write protection is enabled. page write: the 2k device is capable of 16-byte page write. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the fi rst data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen more data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condition (see figure 12 on page 14). the data word address lower four bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than sixteen data words are transmitted to the eeprom, t he data word address will ?roll over? and previous data will be overwritten. the address ?roll over? during write is from the last byte of the current page to the first byte of the same page. the device will acknowledge a write command, but not write the data, if the software or hardware write protection has been enabled. the write cycle time must be observed even when the write protection is enabled. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabl ed, acknowledge polling can be in itiated. this involves send- ing a start condition followed by the dev ice address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a zero allowing the read or write sequence to continue.
10 at34c02b 3417e?seepr?1/07 write protection the software write protection, once enabled, writ e protects only the first-half of the array (00h - 7fh) while the hardware write protection, via the wp pin, is used to protect the entire array. permanent software write protection: the software write protection is enabled by sending a command, similar to a normal write command, to the device which programs the permanent write protect register . this must be done with the wp pin low. the write protect register is programmed by sending a write command with the device address of 0110 instead of 1010 with the address and data bit being don?t cares (see figure 7 on page 10). once the software wr ite protection has been enabled, the device will no longer acknowledge the 0110 control byte. the soft ware write protection cannot be reversed even if the device is powered do wn. the write cycle time must be observed. reversible software write protection : the reversible so ftware write pro- tection is enabled by sending a command, si milar to a normal write command, to the device which programs the reve rsible write protect register. this must be done with the wp pin low. the write protect register is programmed by sending a write command 01100010 with pins a2 and a1 tied to ground or don't connect and pin a0 connected to vhv (see figure 8). the reversible write protection can be reversed by sending a com- mand 01100110 with pin a2 tied to ground or no connect, pin a1 tied to vcc and pin a0 tied to vhv (see figure 9). hardware write protection: the wp pin can be connected to v cc , gnd, or left floating. connecting the wp pin to v cc will write protect the en tire array, regardless of whether or not the software write pr otection has been enabled. the software write protection register cannot be programm ed when the wp pin is connected to v cc . if the wp pin is connected to gnd or left floating , the write protection mode is determined by the status of the software write protect register. figure 7. setting permanent write protect register (pswp) figure 8. setting reversible write protect register (rswp) figure 9. clearing reversible write protect register (rswp) s t a r t s t o p sda line word address data control byte a c k 0 1 1 0 a2 a1 a0 0 a c k a c k = don't care s t a r t s t o p sda line word address data control byte a c k 0110 0 a c k a c k 1 00 = don't care s t a r t s t o p sda line word address data control byte a c k 0110 0 a c k a c k 1 01 = don't care
11 at34c02b 3417e?seepr?1/07 table 6. write protection table 7. vhv note: vhv - vcc > 4.8v table 8. wp connected to gnd or floating pin preamble rw command a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 set pswp a2 a1 a0 0 1 1 0 a2 a1 a0 0 set rswp 00vhv01100010 clear rswp01vhv01100110 min max units vhv 7 10 v wp connected to gnd or floating command r/w bit permanent write protect register pswp reversible write protect register rswp acknowledgment from device action from device 1010 r x x ack 1010 w programmed x ack can write to second half (80h - ffh) only 1010 w x programmed ack can write to second half (80h - ffh) only 1010 w not programmed not programmed ack can write to full array read pswp r programmed x no ack stop - indicates permanent write protect register is programmed read pswp r not programmed x ack read out data don't care. indicates pswp register is not programmed set pswp w programmed x no ack stop - indicates permanent write protect register is programmed set pswp w not programmed x ack program permanent write protect register (irreversible) read rswp r x programmed no ack stop - indicates reversible write protect register is programmed read rswp r x not programmed ack read out data don't care. indicates rswp register is not programmed set rswp w x programmed no ack stop - indicates reversible write protect register is programmed set rswp w x not programmed ack program reversible write protect register (reversible) clear rswp w programmed x no ack stop - indicates permanent write protect register is programmed clear rswp w not programmed x ack clear (unprogram) reversible write protect register (reversible)
12 at34c02b 3417e?seepr?1/07 table 9. wp connected to vcc read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page to the first byte of the first page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current addr ess data word is serially clocked out. to end the command, the microcontroller does not respond with an input zero but does generate a following stop condition (see figure 13 on page 14). random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the mi crocontroller must generate another start condition. the microcontroller now initiate s a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. to end the command, the microcontroller wp connected to vcc command r/w bit permanent write protect register pswp reversible write protect register rswp acknowledgment from device action from device 1010 r x x ack read array 1010 w x x ack device write protect read pswp r programmed x no ack stop - indicates permanent write protect register is programmed read pswp r not programmed x ack read out data don't care. indicates pswp register is not programmed set pswp w programmed x no ack stop - indicates permanent write protect register is programmed set pswp w not programmed x ack cannot program write protect registers read rswp r x programmed no ack stop - indicates reversible write protect register is programmed read rswp r x not programmed ack read out data don't care. indicates rswp register is not programmed set rswp w x programmed no ack stop - indicates reversible write protect register is programmed set rswp w x not programmed ack cannot program write protect registers clear rswp w programmed x no ack stop - indicates permanent write protect register is programmed clear rswp w not programmed x ack cannot write to write protect registers
13 at34c02b 3417e?seepr?1/07 does not respond with a zero but does generate a following stop condition (see figure 14 on page 14). sequential read: sequential reads are initiated by either a current address read or a random address read. after the microcontro ller receives a data word, it responds with an acknowledge. as long as the eeprom rece ives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will ?roll over? and the sequen- tial read will continue. th e sequential read operatio n is terminated when the microcontroller does not respond with a ze ro but does generate a following stop condi- tion (see figure 15 on page 14). permanent write protect re gister (pswp) status: to find out if the regis- ter has been programmed, the same procedure is used as to program the register except that the r/w bit is set to 1. if the device sends an acknowledge, then the perma- nent write protect register has not been programmed. otherwise, it has been programmed and the device is permanently write protected at the first half of the array. table 10. pswp status reversible write protect register(rswp) status: to find out if the regis- ter has been programmed, the same procedure is used as to program the register except that the r/w bit is set to 1. if the sends an device acknowle dge, then the revers- ible write protect register has not been programmed. otherwise, it has been programmed and the device is write protected (reversible) at the first half of the array. figure 10. device address figure 11. byte write pin preamble rw command a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 read pswpa2a1 a0 0 1 1 0 a2a1a0 1
14 at34c02b 3417e?seepr?1/07 figure 12. page write figure 13. current address read figure 14. random read figure 15. sequential read
15 at34c02b 3417e?seepr?1/07 notes: 1. not recommended for new design; please refer to at34c02c datasheet. 2. ?u? designates green package + rohs compliant. 3. ?h? designates green package + rohs compliant, with nipdau lead finish. at34c02b ordering information (1) ordering code package operation range at34c02bn-10su-1.7 (2) at34c02b-10tu-1.7 (2) at34c02by6-10yh-1.7 (3) at34c02bu3-10uu-1.7 (2) 8s1 8a2 8y6 8u3-1 lead-free/halogen-free/ industrial temperature (?40 c to 85 c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) 8y6 8-lead, 2.00 mm x 3.00 mm body, 0.50 mm pitch, ultra thin mini-map, dual no lead package (dfn), (mlp 2x3 mm) 8u3-1 8-ball, die ball grid array package (dbga2) options ?1.7 low voltage (1.7v to 3.6v)
16 at34c02b 3417e?seepr?1/07 packaging information 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
17 at34c02b 3417e?seepr?1/07 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
18 at34c02b 3417e?seepr?1/07 8y6 ? mini-map 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8y6 , 8-lead 2.0 x 3.0 mm body, 0.50 mm pitch, utlra thin mini-map, dual no lead package (dfn) ,(mlp 2x3) c 8y6 8/26/05 notes: 1. this drawing is for general information only. refer to jedec drawing mo-229, for proper dimensions, tolerances, datums, etc. 2. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. common dimensions (unit of measure = mm) symbol min nom max note d 2.00 bsc e 3.00 bsc d2 1.40 1.50 1.60 e2 - - 1.40 a - - 0.60 a1 0.0 0.02 0.05 a2 - - 0.55 a3 0.20 ref l 0.20 0.30 0.40 e 0.50 bsc b 0.20 0.25 0.30 2 a2 b (8x) pin 1 id pin 1 index area a1 a3 d e a l (8x) e (6x) 1.50 ref. d2 e2
19 at34c02b 3417e?seepr?1/07 8u3-1 ? dbga2 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. po8u3-1 a 6/24/03 common dimensions (unit of measure = mm) symbol min nom max note 8u3-1, 8-ball, 1.50 x 2.00 mm body, 0.50 mm pitch, small die ball grid array package (dbga2) a 0.71 0.81 0.91 a1 0.10 0.15 0.20 a2 0.40 0.45 0.50 b 0.20 0.25 0.30 2 d 1.50 bsc e 2.00 bsc e 0.50 bsc e1 0.25 ref d 1.00 bsc d1 0.25 ref 1. this drawing is for general information only. 2. dimension ?b? is measured at maximum solder ball diameter bottom view 8 solder balls b d e top view pin 1 ball pad corner a side view a 2 a 1 4 5 pin 1 ball pad corner 3 1 e 2 6 7 8 d (e1) (d1) 1.
20 at34c02b 3417e?seepr?1/07 revision history doc. rev. date comments 3417e 1/2007 revision history implemented. pg 1: added note: not recommended for new design; please refer to at34c02c datasheet.
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